Antaryami Panigrahi
Antaryami Panigrahi Assistant Professor Department of Electronics & Communictaion Engineering ()
QUALIFICATIONS M.Tech (Microelectronics & VLSI Design), PhD(Ongoing)

CMOS Analog and RF Circuits;

CONTACT: Phone: Email:

1. Circuit Theory by Prof.(Retd.) S. C. Dutta Roy, IIT-Delhi (

2. Basic Electrical Circuits, Prof. N. Krishnapura, Dept of EE, IIT-Madras (

3. Analog Circuit by Prof. Shanti Pavan, Dept of EE, IIT-Madras (

4. Analog Circuits, Prof. N. Krishnapura, Dept of EE, IIT-Madras (


Best Paper Award at 21st International Symposium in VLSI Design and Test (VDAT) in July 2017 held at IIT-Roorkee.


1. Circuit for Power Management.

2. CMOS Circuits for Biomedical implants.

3. Mixed signal systems for SOC




1.   A. Panigrahi, A. Parhi , “A 1.2 V 12.5 MHz 4th order Low Pass Filter with 83dB Stop Band Attenuation Using Low Output Impedance Source Follower in 45nm CMOS ”, IET Circuits, Devices & Systems,  Vol: 12 , Issue 4 ,  pp. 382-389, Aug. 2018  (10.1049/iet-cds.2017.0424 )

2.   A. Panigrahi A, Parhi, “A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS. In: Kaushik B., Dasgupta S., Singh V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, Vol. 711. Springer, Singapore (

3.  A. Panigrahi, A. Parhi, “Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS” Springer, Analog Integrated Circuits and Signal Processing, 92 (1), 159-165, April 2017 (

4.    A. Panigrahi, P. K. Paul, “A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion”, Springer, Analog Integrated Circuits and Signal Processing, May 2013, Volume 75, Issue 2, pp 237-243(


1.  A. Panigrahi, S. Sarania, and Rafwd Brahma, “Design of Low voltage all pMOS Rectifier for Piezo-Electric Energy Harvesting Springer 1st International Conference on Electronic Systems and Intelligent Computing (ESIC 2020), 2nd-4th Mar 2020, NIT-Arunachal Pradesh, India

2.   A. Panigrahi, A. Parhi, “A 0.5V Gain Enhanced bulk driven Pseudo-Differential OTA design in CMOS” IEEE VLSI-SATA 2016, Amritha University, Bangalore, Jan 10-12, 2016.

3.  A. Panigrahi, A. Parhi, “A 0.5V Body Driven Pseudo-Differential OTA for Low Voltage and Low Power Applications” IEEE INDICON 2015, Dec. 2015. [Track : Electronics and Nano Technology]

4. K. Ray, A. Panigrahi, "Design of decimation filters for low pass sigma delta modulator" National Conference on Emerging Global Trends in Engineering and Technology, Don Bosco Univ. Guwahati, 7-8 March 2014.

5. A. Panigrahi, P. K. Paul, “A Novel Bulk-input LP and LV Four Quadrant Analog Multiplier in Weak Inversion”, IEEJ Analog VLSI Work Shop 2011, Indonesia, Bali, Nov 2-4, 2011

Workshop Orgnised:

1.  2 Day Workshop on "VLSI & Embedded Systems” at CIT-Kokrajhar, Feb. 21-22, 2020

# Course Name Code Credits Semester
1 Linear Integrated Circuits EC 403 4 4
Units Chapter Course Materials/Slides