CMOS Analog and RF Circuits
Indian Mythology
1. Circuit Theory by Prof.(Retd.) S. C. Dutta Roy, IIT-Delhi (https://nptel.ac.in/courses/108102042/)
2. Basic Electrical Circuits, Prof. N. Krishnapura, Dept of EE, IIT-Madras (https://nptel.ac.in/courses/117106108/)
3. Analog Circuit by Prof. Shanti Pavan, Dept of EE, IIT-Madras (https://www.youtube.com/playlist?list=PL16BAECF919A0D79C)
4. Analog Circuits, Prof. N. Krishnapura, Dept of EE, IIT-Madras (https://nptel.ac.in/courses/108106084/)
Best Paper Award at 21st International Symposium in VLSI Design and Test (VDAT) in July 2017 held at IIT-Roorkee.
1. Circuit for Power Management.
2. CMOS Circuits for Biomedical implants.
3. Mixed Signal Systems for SoC.
Journals:
1. A. Panigrahi, A. Mathew, "Design of 1.2 V CMOS flipped voltage follower based output-capacitor-less low dropout regulator with improved voltage buffer for impedance attenuation, Springer, Analog Integrated Circuits and Signal Processing, 113, 129–139 Aug. 2022.( https://doi.org/10.1007/s10470-022-02084-1)
2. A. Panigrahi, A. Mathew, "An output-capacitor-less flipped voltage follower based low dropout regulator with improved buffer impedance attenuation in 45 nm CMOS technology", AEU - International Journal of Electronics and Communications, 2022, 154284, ISSN 1434-8411 [https://doi.org/10.1016/j.aeue.2022.154284]
3. A. Panigrahi, A. Parhi , “A 1.2 V 12.5 MHz 4th order Low Pass Filter with 83dB Stop Band Attenuation Using Low Output Impedance Source Follower in 45nm CMOS ”, IET Circuits, Devices & Systems, Vol: 12 , Issue 4, pp. 382-389, Aug 2018 (10.1049/iet-cds.2017.0424 )
4. A. Panigrahi A, Parhi, “A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS. In: Kaushik B., Dasgupta S., Singh V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, Vol. 711. Springer, Singapore (https://doi.org/10.1007/978-981-10-7470-7_61)
5. A. Panigrahi, A. Parhi, “Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS” Springer, Analog Integrated Circuits and Signal Processing, 92 (1), 159-165, April 2017 (https://doi.org/10.1007/s10470-017-0965-8)
6. A. Panigrahi, P. K. Paul, “A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion”, Springer, Analog Integrated Circuits and Signal Processing, Volume 75, Issue 2, pp 237-243, May 2013. (https://doi.org/10.1007/s10470-012-9951-3)
Conferences:
1. A. Panigrahi, G. J. Dutta, S. Bora, K. R. Baruah , M. Paul, "Analysis and Modelling of pMOS based Classical Low Drop Out Regulators: A Time Domain Perspective" 7th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES, formerly IEEE – iNIS) 20-22 Dec 2021, MNIT, Jaipur DOI: 10.1109/iSES52644.2021.00085
2. A. Panigrahi, D. Paul, S. Gupta, S. Chourasia, T. Nath, " A CMOS RF-DC Converter in the GSM Band for RF Energy Harvesting Applications ," IEEE MTT-S International Microwave and RF Conference 2021 (IMaRC 2021) December 17-19, 2021; IIT Kanpur, India DOI: 10.1109/IMaRC49196.2021.9714683
3. A. Panigrahi, A. Mathew "A 1.2V On-chip Output-capacitor-less Low Dropout Regulator based on Flipped Voltage Follower in 45nm CMOS Technology ",16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS); 28-30 June 2021; Montpellier, France DOI: 10.1109/DTIS53253.2021.9525422
4. A. Panigrahi, S. Sarania and R. G. Brahma, "A Low Voltage Rectifier for Piezo-Electric Energy Harvesting Designed in CMOS Technology,"Proc. of IEEE 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 170-174, DOI: 10.1109/DevIC50843.2021.9455897
5. A. Panigrahi, D. Paul, S. Gupta, S. Chourasia, T. Nath “A comparative study of integrated RF to DC power conversion system for RF energy harvesting” , Materials Today: Proceedings, Elsevier, https://doi.org/10.1016/j.matpr.2021.05.633
6. A. Panigrahi, A. Parhi, “A 0.5V Voltage-Combiner based OTA with 60dB gain 250kHz UGB in CMOS using Weakly inverted Transistors” IEEE-iNIS 2016, Dec 19-21, AB-IIIT, Gwalior, India DOI: 10.1109/iNIS.2016.042
7. A. Panigrahi , A. Parhi, “A 0.5V Gain Enhanced bulk driven Pseudo-Differential OTA design in CMOS” IEEE VLSI-SATA 2016,Amritha University, Bangalore, Jan 10-12, 2016. DOI: 10.1109/VLSI-SATA.2016.7593045
8. A. Panigrahi, A. Parhi, “A 0.5V Body Driven Pseudo-Differential OTA for Low Voltage and Low Power Applications” IEEE INDICON 2015, Dec. 2015 DOI: 10.1109/INDICON.2015.7443151
9. K. Ray, A. Panigrahi, "Design of decimation filters for low pass sigma delta modulator" National Conference on Emerging Global Trends in Engineering and Technology, Don Bosco Univ. Guwahati, 7-8 March 2014
10. A. Panigrahi, P. K. Paul, “A Novel Bulk-input LP and LV Four Quadrant Analog Multiplier in Weak Inversion”, IEEJ Analog VLSI Work Shop 2011, Indonesia, Bali, Nov 2-4, 2011
Workshops Organised:
1. Two Day Virtual Workshop/ Webinar on "Intelligent Electronics, Embedded Systems, Communication Technologies” 20-21st November, 2020
2. Two Day Workshop on "VLSI & Embedded Systems” at CIT-Kokrajhar, February, 21-22, 2020
3. Online talk on " The path of UnderGrad to a skilled Engineer: Opportunities & Challenges " 11th June 2022
Professional Membership:
VLSI Society of India
| # | Course Name | Code | Credits | Semester |
|---|---|---|---|---|
| 1 | Linear ICs & Systems | UECE 515 | 3 | 5 |
| Units | Chapter | Course Materials/Slides | ||
UG
2013 Batch: Vijay Manali [CMOS Adders], Rahul, Prateek Pandey, Priyam Kar...[Delta-Sigma Moduators]
2014 Batch: Kanjit Ray , Surojit Das , Alongbar Goyary, Dipendu Kar [Higher Order Delta -Sigma Modulators]
2015 Batch: Liakat Hussain, etal. [Active Filters]
2016 Batch: Sakilur Rahman, Bikram Thapa Chetri, Deep Kumar Machary [AGC/VGA:CMOS Implementation]
2017 Batch: Debabrata Barman, Somesh Ali Sheikh, Dhriti Sundar Basumatary [Design of CMOS OTA and LDO]
2018 Batch: Upasana Das, Tripti, Bikash Sarkar [CMOS Continuous Time Linear Equalizers]
: Gaurav Chetia, Kaushik Kumar [CMOS Analog LDO]
2019 Batch: Monalisha Saikia , Sonu Kumar , Amit Anand, Jyotishna Kurmi , Binita Brahma [Gm-C Filters for RF Receivers]
2020 Batch: Sanjay Sarania, Gautam Kumar Boro, Rafwd Gwra Braham, Dwiden Mushahary [CMOS Rectifiers in Piezo-electric Energy Harvesting]
2021 Batch: Gaurav Jyoti Dutta , Swarnav Bora, Kaushik Roy Baruah, Nabapankaj Bhuyan, Mukul Paul [Design, Analysis of Analog & Digital LDO] &
Digantar Paul, Tushar Nath, Shiwam Gupta, Subham Chourasia [CMOS RF-DC Converters] &
Bishar Patgiri, Rajesh Barman, Rajesh Taid [MCU & Embedded Systems: Gas Leakage Detection]
2022 Batch: Aditya Kumar Thakur, Ashutosh Kumar Sharma, Subham Paul [Design & Verification of UART Controller with System Verilog] &
Soyed Shamim Ahmed, Mohibul Hoque, Vivek Ravidas [Digital control of DC-DC Converters]
2023 Batch: Himjyoti Thakuria, Sayantan Nandi, Deepjyoti Das [Design & Verification of SPI Controller for SoC] &
Abhijeet Kumar, Ananya Nath, Jyotisman Deka [Design & Verification of I2C Controller ]