Dr. Kaushik Chandra Deva Sarma
Dr. Kaushik Chandra Deva Sarma Assistant Professor Department of Instrumentation Engineering ()
QUALIFICATIONS PhD(Tezpur University),M.Tech(Tezpur University)
AREA OF INTERESTS

Research Interests: Semiconductor Devices, Power Electronics, Optoelectronics, Sensors

 

Extra Curricular Interests: Bodybuilding, Power lifting

CONTACT: Phone: 9706490533 Email: kcd.sarma@cit.ac.in
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RESEARCHES:

Session Chair

1. Symposium on VLSI Design and Embedded Computing (VDEC’19), Third International Conference on Computing and Network Communications (CoCoNet’19), September 18-21, 2019, Trivandrum, Kerala, India

2. International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, 2-4 July, 2020

PUBLICATIONS:

 

List of Publications (Selected)

Journal Publications

 

[1]        AK Raibaruah, KCD Sarma” A Potential Model for Parallel Gated Junctionless Field Effect Transistor”, Silicon, Springer                      Nature (2021), DOI.org/10.1007/s12633-020-00890-8

[2]    K C D Sarma, D Deka " An Approach for Potential Modelling of Symmetric Double Gate Junctionless Transistor with Multi Material Gate", Test Engineering and Management, Mattingly Publishing Co. Inc, Vol. 83, No. 3, pages 24553-24563 

[3]       A Talukdar, A K Raibaruah and K C D Sarma " Dependence of Electrical Characterististics of Junctionless FET on Body Material" ,Procedia Computer Science, Elsevier, Vol. 171, No. 6, pages 1046-1053

[4]    K C D Sarma and S. Sharma, "A Method for Reduction of Off State Leakage Cureent in Symmetric DG JLT", Engineering Research Express, IOP Publishing, Vol. 1, No. 1, pages 015034, 2019

[5]      K C D Sarma " A Physics Based Approach for Threshold Voltage Modelling of Symmetric Double Gate  Junctionless Transistor With Multi Material Gate ", Journal of Nanoelectronics and Optoelectronics,       American Scientific Publishers, Vol. 13, No.4, pages 479-483, 2018

[6]    K C D Sarma and S. Sharma, "An Analytical Approach for Drain Current Modelling of A Symmetric Double Gate Junctionless Transistor", Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, Vol. 13, No.9, pages 1332-1339, 2018

[7]     K C D Sarma and S. Sharma, "Carrier Mobility Enhancement of Symmetric Double Gate  Junctionless Transistor”, Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, Vol.12, No.10, 2017

[8]    K C D Sarma and S. Sharma, "An Approach for Complete 2-D Analytical Potential Modelling of Fully Depleted Symmetric Double Gate Junction Less Transistor", Journal of Computational Electronics, Springer, Vol. 14, No. 3, pages 717-725, 2015

[9]    K C D Sarma and S. Sharma, "Scale Length Determination of Gate All Around (Regular Hexagonal Cross Section) Junctionless Transistor",  International Journal of Applied Engineering Research (IJAER) , Vol. 10, No. 2, pages 4751-4762, 2015

[10]      K C D Sarma, A Mallik, A Bhatnagar "Microcontroller Based Optical power meter for Lab Applications", Journal of Instrument Society of India, Vol. 40, June,2010.

 

[11]    K C D Sarma and S. Sharma, " Corner Effect in JLT with A Proposal for Reduction" International Journal of Engineering and Advanced Technology (IJEAT) (Accepted)

 

Conference Publications

 

[1]     A Talukdar and K C D Sarma " An Analytical Potential Model for Normally on Double gate Junctionless Field Effect Transistor", In International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, pages 464-468, 2-4 July, 2020 

[2]     A Baro and K C D Sarma " Study on Electrical Characteristics of Double gate Junctionless Field Effect Transistor with Triangular Shaped Spacer", In International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, pages 601-603, 2-4 July, 2020 

[3]    A K Raibaruah, A Talukdar and K C D Sarma " Undoped Junctionless Field Effect Transistor", In International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, pages 725-727, 2-4 July, 2020 

[4]     A K Raibaruah and K C D Sarma " Parallel Gated Junctionless Field Effect Transistor", In International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, pages 178-181, 2-4 July, 2020 

[5]    N Das and K C D Sarma " Surrounded Channel Junctionless Field Effect Transistor", In International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, pages 608-610, 2-4 July, 2020 

[6]     N Das and K C D Sarma " Depletion Width Modelling of Surrounded Channel Junctionless Field Effect Transistor", In International Conference on Computational Performance Evaluation (ComPE), North Eastern Hill University, Shillong, India, pages 611-614, 2-4 July, 2020 

[7]     K C D Sarma and S. Sharma, "Scale Length Determination of Gate All Around (Regular Pentagonal Cross Section) Fully Depleted Junctionless Transistor", In IEEE  International Conference on Advances in Engineering and Technology Research (ICAETR), Dr. Virendra Swarup Group of Institutions,  Unnao, UP, pages 1-5, 1-2 August,2014

[8]    K C D Sarma and S. Sharma, "Scale Length Determination of Gate All Around (Octagonal Cross Section) Junctionless Transistor", In International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), NIT, Meghalaya, pages 1-5,  29-30th January ,2015

[9]       K C D Sarma and S. Sharma, "A Method for Determination of Depletion Width of Single and Double Gate Junction Less Transistor", In International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), NIT, Meghalaya,  pages 114-119, 29-30th January ,2015

[10]   K C D Sarma, S. Sharma and C. Hazarika, "Scale Length Determination of a Fully Depleted Surrounding Gate (Rectangular Cross Section) Junction Less Transistor", In International Conference on Electrical, Electronics, Signals, Communication & Optimization-EESCO, pages 1-4, 24-25 Jan-2015,Visakhapatnam,  Andhra Pradesh, India

[11]    K C D Sarma "A Study on The Effect of Source-Drain Length on Device Performane of Junctionless Transistor", In 580th International Conference on Innovative Engineering Technologies (ICIET), 1-2 April, Dubai, UAE

Book Chapter

[1]   Sarma, K. C. D. and Sharma, S. A Review on Evolution of MOSFET with Special Emphasis on Junctionless Transistor, In Ajay Kumar, B. S. and Sarkar, D., editors, Advanced Engineering Research and Applications, ISBN:978-93-84443-48-1, Research India Publications.

 

 

COURSE ENGAGEMENT:
# Course Name Code Credits Semester
STUDENTS SUPERVISED:

M.Tech - 3 Completed

Ph.D. - 4 On going